Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include hundreds of millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A fin field effect transistor (FinFET) is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. In a FinFET the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence a very efficient layout, can be achieved without substantially increasing the area of the substrate surface required by the transistor. Additionally, the 3 dimensional structure allows the use of undoped channels, which improves short channel control, reduces leakage, and improves carrier mobility over doped channels.
There are various methods of producing FinFET IC's, including the use of semiconductor on insulator (SOI) substrates. Alternatively, a FinFET can be fabricated from a bulk semiconductor substrate, which has a lower cost compared to an SOI substrate. The fins are formed from a bulk semiconductor substrate, so the fins and the base of the substrate are one continuous component. When using a bulk semiconductor substrate, a dielectric insulator is typically used between adjacent fins to determine the active fin height. The insulator is typically applied to fill the area between the fins and to extend over the top of the fins. Flowable oxides (known by the trademark FOX®), high aspect ratio processes (HARP), enhanced high aspect ratio processes (eHARP), and other techniques can be used to fill the area between the fins. However, if the fins have a high aspect ratio, such as when the fin to fin distance is about 20 nanometers (nm) or less, the options for a void-free fill between the fins is limited primarily to FOX®. FOX® utilizes a steam anneal for densification, which may oxidize the fins. Also, the wet etch resistance of FOX® is less than that of thermal oxide by a factor of about 1.5 to 2, and higher wet etch resistance may be desired. The upper surface of the insulator, which is over the fin tops, is then planarized, which may use chemical mechanical planarization (CMP). The insulator is then recessed by wet or dry etch to a desired height below the fin tops, so a portion of the fins extend over the insulator. The portions of the fins that extend over the insulation are then further processed to form FETs.
The etching process is not perfectly uniform, so the height of the insulator between the fins varies from one location to another. The etching process also leaves a rough surface, so the top of the insulator is not smooth. The variations in insulation height change the effective width of the FinFET channel, because the channel is formed along the vertical sidewalls of the fin. The FinFET's conductance and transconductance is proportional to the channel width, so the transistor conductance and transconductance varies from one fin to the next as the height of the insulation varies. Furthermore, the exact depth of the etching cannot be precisely controlled, so the variation in the conductance and transconductance from one FET to the next is not controlled or known.
Accordingly, it is desirable to provide a bulk FinFET IC that overcomes the problem of varying transconductance from one FET to the next. In addition, it is desirable to provide methods for fabricating a FinFET IC on a bulk semiconductor substrate that reduces the variation in transconductance from one FET to the next. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.